TSMC isn't hesitant to share extreme details of its roadmap up to 2023: TSMC has planned total six nodes and five packaging techniques.Post N7 node is TSMC’s N7P process, which is a DUV-based optimization of the former to deliver either a 7% performance improvement, or a 10% power efficiency gain.The N7+ is TSMC’s first fabrication process to use EUV for certain layers in the chip.
TSMC’s first true EUV implementation for the N7 is the fab’s N6 processing node which is design and IP compatible with the N7 and also provides an 18% density improvement over chips made by the N7+. N6 is scheduled for risk production in 2020. Finally, the N5 node will be twice as dense (171.3MTR/mm²) as the N7, with either 15% more performance or 30% less power consumption over the N7. Next, FEOL and MOL optimizations will lead to the N5P. The N5P will improve performance by 7% or power consumption by 15%.
Source:TSMC’s True EUV Lithography Will Be On N5 Node For 2x Transistor Density, (LINK)
By Abhishekkumar Thakur