TSMC’s Joint-CEO Wei Zhejia Announces Mass Production of 5nm WoW Built Chips In 2021 After Completing World’s Frist 3D IC Package. This shift will allow its customers to ‘stack’ multiple CPUs or GPUs on one another inside a single package – effectively doubling the number of transistors. To achieve this, TSMC will connect the two different die wafers using TSVs (Through Silicon Vias). TSVs are essentially 10-micron holes that facilitate transfer between the two stacked chips. TSMC has developed the technology in a partnership with California based Cadence Design Systems, and the technology is an extension of the company’s InFO (Integrated Fan-out) and CoWoS (Chip-on-Wafer-on-Substrate) 3D chip production techniques.
Source: wccftech.com LINK
by Abhishekkumar Thakur