Friday, May 4, 2018

TSMC ramps 7nm and details technology roadmap including EUV for early 2019

[EE Times] TSMC announced that it is in volume production with a 7-nm process and will have a version using extreme ultraviolet (EUV) lithography ramping early next year. In addition, it gave its first timeline for a 5-nm node and announced a half-dozen new packaging options.
TSMC is in volume production of 7-nm chips today with more than 50 tapeouts expected this year. It’s making CPUs, GPUs, AI accelerators, cryptocurrency mining ASICs, networking, gaming, 5G, and automotive chips.

The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density compared to the 16FF+ generation two steps before it. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.

Full article : EE Times LINK 
According to TSMC, their 7nm Fin Field-Effect Transistor (FinFET) process technology provides the industry's most competitive logic density and sets the industry pace for 7nm process technology development by delivering 256Mb SRAM with double-digit yields in June 2016. Risk production started in April 2017.
TSMC's 7nm Fin Field-Effect Transistor (FinFET) process technology []

TSMC's 5 nm and a the later version of 7 nm FinFET will adopt EUV Lithography for more critical layers to reduce multi-pattern process complexity while achieving aggressive die area scaling. 
As reported in April, Intel has pushed out their 10 nm node to some time in 2019 due to yield issues in multiple patterning (LINK). The Intel 10 nm is comparable in transistor density too the Foundry 7 nm nodes (see graph below), which mean that by this announcement TSMC has taken over the lead from Intel in scaling.
Intel's Mark Bohr also declared the standard node inadequate and proposed that transistor density be used as a metric instead. However, Scotten Jones has calculated transistor densities for the manufacturers' processes using the Intel definition. When these are plotted against standard nodes, the densities are exactly what one would expect from the standard node values. The Intel transistor densities are values disclosed by Intel, rather than calculated. [Seeking Alpha, LINK]

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