Showing posts with label 10nm. Show all posts
Showing posts with label 10nm. Show all posts

Saturday, October 27, 2018

Intel reports progress on 10 nm

[EETimes LINK] Intel said that it’s making progress on improving 10-nm yields and reiterated its pledge to have 10-nm chips shipping by the 2019 holiday season.

In a conference call with analysts following a financial report that beat analysts’ expectations for the 12th straight quarter, Venkata (Murthy) Renduchintala, president of Intel’s Technology, Systems Architecture and Client Group, said that 10-nm yields are now tracking roughly in line with what the company experienced at the 14-nm node when it prepared to make that transition. 


“We’re still very much reinforcing and reaffirming our previous guidance that we believe that we’ll have 10 nm shipping by holiday of 2019,” said Renduchintala. “And if anything, I feel more confident about that at this call than I did on the call a quarter ago. So we’re making good progress, and I think we’re making the quarter-on-quarter progress that’s consistent with prior generations having reset the progress curve.”

Source : EETimes LINK

Sunday, September 30, 2018

Intel is investing $1 Billion In 14nm to meet demand

According to wccftech.com [LINK] Intel 10nm is on track for HVM 2019 and they are investing an additional $1 billion in 14nm production ramp.

 
"We are clearly entering into uncharted territory as far as the x86 market goes, with demand at an all-time high, Intel struggling to get its 10nm process out and AMD as competitive as ever. Intel’s 14nm process has been seeing incredible demand and the company will be putting in an additional $1 billion to ramp production up. One key thing to note here is that hardware for 14nm and 10nm fabrication is about the same – which essentially means that there is very little opportunity cost for chasing 14nm production at this time. Simply put, this update was great news for Intel shareholders."

To address this challenge Intel will:
  • Invest a record $15 billion in capital expenditures in 2018, up approximately $1 billion from the beginning of the year. We’re putting that $1 billion into our 14nm manufacturing sites in Oregon, Arizona, Ireland and Israel. This capital along with other efficiencies is increasing our supply to respond to your increased demand.
  • Improve yields for 10nm and expect volume production in 2019.


Sunday, June 3, 2018

The Foundries are aiming at AI chip orders in China with 10/14nm advanced process technologies

[Cage Chao, Taipei; Jessie Shen, DIGITIMES] Semiconductor Manufacturing International (SMIC), and the China-based production subsidiaries of both Globalfoundries and United Microelectronics (UMC) are looking to expand their advanced node offerings for the China market to include 10/14nm as they vie for orders from the local AI chip supply chain, according to industry sources.

Taiwan Semiconductor Manufacturing Company's (TSMC) newly-established Nanjing fab, which has entered directly 16nm FinFET chip production since April 2018, has enjoyed robust orders from China-based AI chip developers eager to accelerate the adoption of advanced process technologies, the sources indicated.

China-based foundries including SMIC, and Globalfoundries' and UMC's production subsidiaries locally have informed their customers they will be capable of providing 10/14nm node manufacturing starting the second half of 2018 or 2019, the sources disclosed.These foundries are looking to catch up with TSMC in China's market for advanced process technologies, the sources said.

Source: Digi Times LINK

Friday, April 27, 2018

Intel shifts high volume 10 nm shipments to 2019 due to yield issues from multi-patterning

As reported by Reuters [LINK], Intel bet the earnings expectations for the first quarter driven by the biggest-ever quarterly jump in its data centre business and small-but-steady growth in its personal computer business.However, Intel also announced that they are pushing out volume production of their 10 nm Logic process to 2019, which was most recently announced for the 2nd half of 2018. during the 1Q 2018 earnings conference calls more details were given:

[Seeking Alpha, LINK] "We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, but the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.

Moore's Law is essential to our strategy and our product leadership. It continues to create significant value for Intel and our customers. While it's taking longer and costing more to deliver and yield advanced process technologies, we are able to optimize our process and products within the node to deliver meaningful performance improvements.

For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70% since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it's that product leadership that ultimately matters most to our customers and end users."

Brian M. Krzanich - Intel Corp.

Earnings call slides [Seeking Alpha, LINK]

In the Q&A Mr. Krzanich elaborated on the reason behind the 10 nm push out and he explained how it is mainly due to yield issues coming from multiple patterning (SADP and SAQP):

- Intel have 10 nm product and process leadership and are shipping 10 nm products today. 
- Those are the densest, highest performing products out there.
- Intel is slowing the ramp down to fix yield issues related to patterning.
- In multi-multi-patterning (SAQP) there are six layers of patterning to produce a feature. 
- Intel understand the yield issues, which are tied to 10 nm being the last technology tied to not using EUV and the amount of multi-patterning and the effects of that on defects.


Intel’s 10 nm Platform Process was presented in detail at the IEDM 2017 (Dec 2017) “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects” and you may study the details in this excellent article by Dick James [Solid State Technology, LINK]

Media coverage:
 
The Register